Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation

The availability of wide-band low-power frequency dividers is fundamental in transceivers for emerging mm-wave applications. Up to date injection locked topologies have been investigated for very high frequency operations but at the price of large area and limited frequency range. In this work, we investigate a new class based on dynamic latches with load modulation. The proposed latches can be viewed as the evolution of classic static CML latches where the regenerative cross-coupled pair is removed for minimum parasitic at output nodes, i.e., maximum speed, and loads are modulated by the input clock for maximum charge retention during hold times. A time-domain circuit inspection aimed at deriving analytical expressions for maximum and minimum operation frequency and providing guidelines for optimum design is reported. Prototypes of dividers by 4, realized in 32 nm bulk CMOS, operate between 14 GHz and 70 GHz, demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8 mW of maximum power consumption and 55 ×18 μm2 occupied area

A 6.5mW Inductorless CMOS Frequency Divider by 4 Operating up to 70GHz

Differential amplifiers working as dynamic CML latches are proposed to realize compact, low power millimeter-waves frequency dividers. An inductorless divider by 4 realized in 65nm CMOS technology demonstrates an operating frequency programmable from 20GHz to 70GHz with a maximum power dissipation of 6.5mW from 1V supply

A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP

A design methodology for interstage and output matching networks for wide-band Power Amplifiers for wireless applications is proposed. Leveraging wideband inductively coupled resonators, we apply Norton transformations for impedance matching. A two-stage differential PA with neutralized common source stages has been realized in 28 nm CMOS using low-power devices. The PA delivers 13 dBm saturated output power over 40-67GHz bandwidth with a peak power-added efficiency of 16% without power combining. To the best of author's knowledge, the presented PA shows state-of-the art performances with the largest fractional bandwidth among mm-wave PAs reported so far

A 40\u201367 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP

Pushed by the availability of large fractional bandwidths, many well-established applications are focusing mm-wave spectrum for product deployment. Generation of broadband power at mm-waves is challenging because a key target such as the efficiency trades with the gain-bandwidth (GBW) product. The major limit is the capacitive parasitics at the interstage between driver and power devices. The latter are designed with a large form factor so as to deliver the desired output power and are commonly biased in class-AB to achieve high drain efficiency, penalizing GBW. In this paper, a design methodology for interstage and output matching networks targeting large fractional bandwidth and high efficiency is proposed. Leveraging inductively coupled resonators, we apply Norton transformations for impedance scaling. In both networks, topological transformations are employed to include a transformer, achieve the desired load impedance and minimize the number of components. A two-stage differential PA with neutralized common source stages has been realized in 28 nm CMOS using low-power devices. The PA delivers 13 dBm saturated output power over the 40\u201367 GHz bandwidth with a peak power-added efficiency of 16% without power combining. To the best of author's knowledge, the presented PA shows state-of-the-art performances with the largest fractional bandwidth among bulk CMOS mm-wave PAs reported so far

A mm-wave quadrature VCO based on magnetically coupled resonators

Search of a compact quadrature generator at around 60GHz with low phase noise at moderate power is the topic of this work. Discarding a double-frequency VCO followed by dividers-by-two given the high frequency range of operation, the most suitable topology borrowed by RF solutions is represented by cross-coupled LC voltage-controlled oscillators. However, the oscillation frequency dependence on the biasing current makes it susceptible to phase noise, close-in in particular. At mm-Waves, this is exacerbated by core devices of small dimensions to such an extent that 1/f noise remains dominant up to more than ~10MHz, making it unsuitable for stringent applications. On the contrary a ring of two VCOs magnetically coupled to each other has an oscillation frequency dependence on inter-stage passive components only, low 1/f noise together with good quadrature accuracy. The quadrature oscillator has been realized in a 65nm CMOS technology and prototypes show the following performances: 56-to-60.3GHz tunable oscillation frequency, phase noise better than -95dBc/Hz at 1MHz offset in the tuning range, 1.5° maximum phase error while consuming 22mA from a 1V supply